The present invention relates to a lateral field effect transistor (hereinafter referred to as "MOSFET") and, more particularly, to a lateral MOSFET with low on-resistance.
It is desirable to lower the on-resistance of the devices incorporated in electronic instruments as well as their power consumption and power supply voltage in order to make them portable. Switching elements with very low on-resistance of less than several tens m.OMEGA. are especially desirable. Lateral field effect transistors are suitable for this purpose because their on-voltage is low, especially in a small current range, as they do not have p-n junctions which a current must traverse.
FIG. 10 is a cross section of a lateral field effect transistor. The MOSFET chip 100 shown has a metal oxide film semiconductor (MOS) type gate. FIG. 11 is a top plan view of the MOSFET of FIG. 10.
Referring now to FIG. 10, a p-type well region 103 is formed on a p-type substrate 101. A p-type base region 104 is formed in a surface layer of the p-type well region 103. An n-type source region 105 is then formed in a surface layer of the p-type base region 104. An n-type offset region 106 is also formed in the surface layer of the p-type well region 103. A narrow channel separates the n-type offset region 106 from the p-type base region 104. A thick oxide film (LOCOS) 112 is formed on a part of the n-type offset region 106. An n-type drain region 107 is formed on a part of the n-type offset region 106 away from the p-type base region 104.
A poly-crystalline silicon gate electrode 109 is fixed via a gate oxide film 108 to the region extending between the n-type source region 105 and the n-type offset region 106. A source electrode 110 is fixed commonly to the n-type source region 105 and the p-type base region 104 via a source contact 114. A drain electrode 111 is fixed to the n-type drain region 107 via a drain contact 115.
When a positive signal is fed to the gate electrode 109 of the lateral MOSFET while a voltage is applied between the drain electrode 111 and source electrode 110, an inversion layer is created in the surface layers of the p-type base region 104 and the p-type well region 103. As the inversion layer is created, a current flows between the drain electrode 111 and source electrode 110. When the signal is removed from the gate electrode 109, the inversion layer vanishes and the current flow between the drain electrode 111 and source electrode 110 is interrupted.
In MOSFETs, the n-type source region 105 and the n-type drain region 107 are often formed in stripes so as to elongate the opposed facing length of the n-type source region 105 and the n-type drain region 107. A zone delimited by the line F--F' and the line G--G' of FIG. 10 is inverted and repeated many times on the substrate.
Respective electrodes fixed to each zone are formed in stripes and are connected at their ends forming combtooth-like electrodes. In some cases, the n-type source region 105 and the n-type drain region 107 are often shaped into combtooth-like regions. The left side part of the p-type base region 104, i.e., the outermost p-type base region in FIG. 10, is covered with the thick LOCOS film 112. A withstand voltage structure that sustains the breakdown voltage of the device is located on the further left side of the figure. The withstand voltage structure, however, is not illustrated and its explanation is omitted since the present invention does not relate to the withstand voltage structure.
Referring now to FIG. 11, a region surrounded by dotted lines indicates the source contact region 114 contacting the n-type source region 105 or the drain contact region 115 contacting the n-type drain region 107. A region surrounded by bold solid lines indicates the source electrode 110 or the drain electrode 111. A source pad 116 is formed at the end of the source electrode 110. A drain pad 117 is formed at the end of the drain electrode 111. Both the source pad 116 and the drain pad 117 are not covered by a passivation film in order to facilitate wire bonding. In addition, a gate pad 124 is connected with the gate electrode 109.
As the on-resistance is lowered, the on-resistance midway to the electrode for external wiring, i.e., the ratio of the wiring resistance to the total on-resistance is not negligible any more. To solve this problem, the metal wiring is widened toward the downstream side so as to reduce the wiring resistance. R. K. Williams et al., "Design and Operation of a Fully Integrated BiC/DMOS Head-Actuator PIC for Computer Hard-Disk Drives," IEEE Transaction of Electron Devices, Vol. 38, No. 7, p. 1590 (1991). However, an on-resistance of less than 10 m.OMEGA. would be difficult to obtain without increasing the chip area, which, in turn, increases the cost.
In view of the foregoing, it is desirable to provide a lateral field effect transistor having low on-resistance while maintaining the same chip area.